The growing demand for portable electronics, Internet of Things (IoT) devices, artificial intelligence accelerators, and battery-powered embedded systems has increased the need for energy-efficient processor architectures. Modern processors must deliver high computational performance while minimizing power consumption and thermal dissipation. In VLSI systems, processor energy efficiency directly influences battery life, operating cost, and system reliability. This paper presents the design of an energy-efficient processor architecture that incorporates clock gating, dynamic power management, optimized arithmetic units, and low-power pipeline techniques to reduce energy consumption without significantly affecting performance. The proposed architecture utilizes efficient resource allocation and adaptive processing techniques to minimize switching activity and leakage power. The processor is modeled using Verilog HDL and synthesized using Xilinx Vivado. Experimental results demonstrate reductions in power consumption while maintaining acceptable throughput and hardware utilization. The proposed design is suitable for modern low-power computing applications including IoT devices, wireless sensor networks, and edge-computing platforms.