DESIGN OF A 4-BIT MAGNITUDE COMPARATOR BASED ON PASSS TRANSISTOR, TRANSMISSION GATE AND CONVENTIONAL CMOS LOGIC
— A 4-bit magnitude comparator is a digital circuit used to compare two 4-bit binary numbers and determine whether one number is greater than, equal to, or less than the other. In this project, the comparator is designed and implemented using three different logic styles: conventional CMOS logic, pass transistor logic, and transmission gate logic. The main objective is to analyse and compare the performance of these design techniques in terms of power consumption, speed, and area. Conventional CMOS logic provides reliable operation with good noise immunity, while pass transistor logic reduces transistor count and improves speed. Transmission gate logic combines the advantages of both by offering better signal integrity and efficient switching. The circuits are designed and simulated to evaluate their functionality and performance. The results show the trade-offs between different logic styles, helping in selecting an optimal design for low-power and high-speed digital applications.
Harika, K., Akshitha, J. & Lakshmi, K. S. (2026). Design of a 4-Bit Magnitude Comparator Based on Passs Transistor, Transmission Gate and Conventional CMOS Logic. International Journal of Science, Strategic Management and Technology, 02(04). https://doi.org/10.55041/ijsmt.v2i4.229
Harika, K., et al.. "Design of a 4-Bit Magnitude Comparator Based on Passs Transistor, Transmission Gate and Conventional CMOS Logic." International Journal of Science, Strategic Management and Technology, vol. 02, no. 04, 2026, pp. . doi:https://doi.org/10.55041/ijsmt.v2i4.229.
Harika, K.,J. Akshitha, and K. Lakshmi. "Design of a 4-Bit Magnitude Comparator Based on Passs Transistor, Transmission Gate and Conventional CMOS Logic." International Journal of Science, Strategic Management and Technology 02, no. 04 (2026). https://doi.org/https://doi.org/10.55041/ijsmt.v2i4.229.
2.Yan, “Design and optimization of CMOS based 4-bit comparator,” Applied and Computational Engineering, vol. 41, pp. 29–42, 2024.
3.R. Veni Shetty and A. K. Chidra, “Design of power efficient, high-speed 4-bit comparator in UMC 180 nm technology,” Engineering and Applied Science Research, vol. 48, no. 1, pp. 40–47, 2021.
4.K. Sharma and R. Sharma, “Area and power efficient 4-bit comparator design,” International Journal of Engineering Research and Technology (IJERT), 2017.
5.Singh and C. Goel, “An optimal approach to design 4-bit reversible power efficient comparator,” IJERT, 2016.
6.H. Bhuyan, M. M. H. Riyadh, M. S. Hossain, and M. A. Rahman, “Design and simulation of low power high-speed 4-bit magnitude comparator using CMOS,” 2020.
7.K. Sarkar and D. Saha, “Design of low power magnitude comparator using GDI technique,” IEEE Conference on Devices for Integrated Circuit (DevIC), 2017.
8.N. Mukherjee, S. Panda, and B. Maji, “Design of low power 12-bit magnitude comparator,” IEEE DevIC, 2017.
9.Alioto and G. Palumbo, “Analysis and comparison of high-speed CMOS comparators,” IEEE Transactions on Circuits and Systems, 2002.
10.K. Mathew et al., “A low-power high-speed comparator for ADC applications,” IEEE Journal of Solid-State Circuits, 2008.