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DESIGN OF A LOW-POWER TRUE SINGLE-PHASE CLOCKED FLIP-FLOP FOR HIGH-PERFORMANCE VLSI SYSTEMS

AUTHORS:
Bhimireddi Lakshmi Parvathi
Mentor
K. V. S. Ganesh , Dr. R. Prasad Rao
Affiliation
Department of ECE Avanthi institute of engineering & Technology Makavarapalem, Visakhapatnam, India
CC BY 4.0 License:
This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract

Flip-flops (FFs) are fundamental sequential elements in digital systems, and their power consumption significantly influences overall system efficiency. This work presents an energy-efficient True Single-Phase Clocked (TSPC) flip-flop designed for high-performance and low-power applications. The proposed design incorporates an input-aware conditional pre-charge mechanism, which activates only when required, thereby reducing unnecessary switching activity and dynamic power consumption. Furthermore, transistor-level optimization and floating node analysis are employed to enhance energy efficiency without incurring substantial area overhead. Post-layout simulation results demonstrate that the proposed flip-flop achieves a power reduction of up to 84.37% compared to a conventional Transmission Gate Flip-Flop (TGFF) at a 1 V supply voltage under 10% switching activity. The power savings further improve to 98.53% under zero data activity conditions. In addition to power efficiency, the design achieves a 17.6% reduction in clock-to-Q delay, making it suitable for high-speed applications. These results highlight the effectiveness of the proposed TSPC flip-flop for next-generation low-power VLSI systems.

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Parvathi, B. L. (2026). Design of a Low-Power True Single-Phase Clocked Flip-Flop for High-Performance VLSI Systems. International Journal of Science, Strategic Management and Technology, 02(05). https://doi.org/10.55041/ijsmt.v2i4.650

Parvathi, Bhimireddi. "Design of a Low-Power True Single-Phase Clocked Flip-Flop for High-Performance VLSI Systems." International Journal of Science, Strategic Management and Technology, vol. 02, no. 05, 2026, pp. . doi:https://doi.org/10.55041/ijsmt.v2i4.650.

Parvathi, Bhimireddi. "Design of a Low-Power True Single-Phase Clocked Flip-Flop for High-Performance VLSI Systems." International Journal of Science, Strategic Management and Technology 02, no. 05 (2026). https://doi.org/https://doi.org/10.55041/ijsmt.v2i4.650.

References
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