LOW POWER 8-BIT ALU DESIGN USING M-GDI TECHNIQUE
DOI: 
SHARE THIS ARTICLE
DOWNLOAD ARTICLE
REVIEW REPORT
CITE THIS ARTICLE
This paper presents the design and implementation of an 8-bit Arithmetic Logic Unit (ALU) using Modified Gate Diffusion Input (M-GDI) technique. The proposed design focuses on reducing power consumption, propagation delay, and area compared to conventional CMOS logic. The ALU performs multiple operations such as AND, OR, XOR, NAND, NOR, NOT, addition, and subtraction using an efficient 8:1 multiplexer structure. The design is implemented and simulated using Cadence tools. The design is implemented and simulated using Cadence tool. Results show that the M-GDI based ALU achieves significant improvement in speed and power efficiency, making it suitable for modern VLSI applications. The ALU is developed and simulated using Cadence Design Systems with the 45 GDK (Generic Design Kit).
Keywords
Article Information
Article Metrics
HOW TO CITE
Copy
Srijana, G., Harilatha, M. & D.Varsha, (2026). Low Power 8-Bit Alu Design using M-GDI Technique. International Journal of Science, Strategic Management and Technology, 02(04). https://doi.org/10.55041/ijsmt.v2i4.621
Srijana, G., et al.. "Low Power 8-Bit Alu Design using M-GDI Technique." International Journal of Science, Strategic Management and Technology, vol. 02, no. 04, 2026, pp. . doi:https://doi.org/10.55041/ijsmt.v2i4.621.
Srijana, G.,M. Harilatha, and D.Varsha. "Low Power 8-Bit Alu Design using M-GDI Technique." International Journal of Science, Strategic Management and Technology 02, no. 04 (2026). https://doi.org/https://doi.org/10.55041/ijsmt.v2i4.621.
References
2.Sree Reddy, K. V. Koteswara Rao, “32 – Bit Arithmetic And Logic Unit Design With Optimized Area And Less Power Consumption By Using Gdi Technique”, International Journal Of Research In Computer Applications And Robotics, Vol.3 Issue.4, Pg.: 51-66, April 2015.
3.Vijaya Shekhawat, Tripti Sharma and Krishna Gopal Sharma, “2- Bit Magnitude Comparator using GDI Technique”, IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), May 09-11, 2014, Jaipur, India.
4.Uma, “4-Bit Fast Adder Design: Topology and Layout with Self- Resetting Logic for Low Power VLSI Circuits”International Journal of Advanced Engineering Sciences and Technology, Vol No. 7, Issue No. 2, 197 205, 2011.
5.Uma and P. Dhabachelvan “Analysis on Impact of Behavioral Modeling in Performance of Synthesis Process The second International Conference on Advances in Computing and Information Technology, July 2012, Published in Advances in Intelligent Systems and Computing book series of Springer.
6.“Design of High Speed, Area Optimized and Low PowerArithmetic and Logic Unit”, Advances in Industrial Engineering and Management,Vol.6, No. 1 (2017), 26-31 by Md.Afreen Begum and S. Sweta
7.“Modified Gate Diffusion Input Technique: A New Techniqu for Enhancing Performance in Full Adder Circuits”, Procedia Technology 6 ( 2012 ) 74 –81 by P.Dhabachelvan and R.Uma.
8.Pankaj Verma , Ruchi Singh and Y. K. Mishra, “Modified Gdi Technique - A Power Efficient Method For Digital Circuit Design”, International Journal of Advanced Technology in Engineering and Science, Volume No.01, Issue No. 10, October 2013.
9.Raja, K. Thanushkodi and T. Hemalatha, “Comparative Analysis of Various Low Power Clock Gating Design for ALU,” IEEE International Conference on Electronics and Communication Systems (ICECS), pp. 1-5, February 2014.
10.Zahid Ali Siddiqui, Park Hui-Jong and A. Lee Jeong, “Area-Time Efficient Self-Checking ALU based on Scalable Error Detection Coding ,” IEEE 2013 Euromicro Conference on Digital System Design (DSD), pp. 870-877, September 2013.
Ethics and Compliance
Indexed In
Similar Articles
Previous Article
