PERFORMANCE ANALYSIS OF CARRY LOOK-AHEAD ADDER USING HYBRID FULL ADDER IN 45NM TECHNOLOGY
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This paper presents the design and performance analysis of a Carry Look-Ahead (CLA) adder using a Hybrid Full Adder (HFA) in 45 nm CMOS technology, aimed at achieving high speed and low power operation. The proposed design combines parallel carry generation of the CLA architecture with a reduced transistor hybrid full adder to minimize propagation delay and power consumption. The circuit is designed and simulated using Cadence Virtuoso, and key parameters such as delay, power, and power-delay product (PDP) are evaluated. Simulation results show that the proposed CLA adder achieves a propagation delay of 0.42 ns, power consumption of 18.6 µW, and PDP of 7.81 fJ, with improvements of approximately 32% in delay and 27% in power compared to conventional designs. These results demonstrate that the proposed architecture provides an efficient trade-off between speed, power, and area, making it suitable for high-performance VLSI applications.
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Shivani, K., Harika, G. & Pranavi, E. (2026). Performance Analysis of Carry Look-Ahead Adder using Hybrid Full Adder in 45nm Technology. International Journal of Science, Strategic Management and Technology, 02(04). https://doi.org/10.55041/ijsmt.v2i4.226
Shivani, Kovvuri, et al.. "Performance Analysis of Carry Look-Ahead Adder using Hybrid Full Adder in 45nm Technology." International Journal of Science, Strategic Management and Technology, vol. 02, no. 04, 2026, pp. . doi:https://doi.org/10.55041/ijsmt.v2i4.226.
Shivani, Kovvuri,Gobathuni Harika, and Edugu Pranavi. "Performance Analysis of Carry Look-Ahead Adder using Hybrid Full Adder in 45nm Technology." International Journal of Science, Strategic Management and Technology 02, no. 04 (2026). https://doi.org/https://doi.org/10.55041/ijsmt.v2i4.226.
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