INTELLIGENT REINFORCEMENT LEARNING-BASED FLOOR PLANNING FRAMEWORK FOR MULTI-OBJECTIVE OPTIMIZATION IN VLSI PHYSICAL DESIGN
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A Mamatha
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Department Of ECE, SVS Group of Institutions, Hanumakonda, Telangana
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Abstract
The increasing complexity of modern Very LargeScale Integration (VLSI) systems has significantly elevated the importance of efficient chip floor planning during the physical design stage. Traditional floor planning approaches often struggle to meet stringent requirements related to area utilization, wirelength minimization, power efficiency, thermal management, and timing constraints, particularly in advanced technology nodes. Recent advancements in Artificial Intelligence (AI) and Machine Learning (ML) have introduced new opportunities for automating and optimizing chip floor planning processes. AI-driven optimization techniques can analyze large design spaces, learn placement patterns, and generate efficient floorplans within significantly reduced computation times. This paper presents a comprehensive study of AI-based floor planning methodologies and proposes an Intelligent Reinforcement Learning Floor planning Framework (IRLFF) for VLSI systems. The proposed framework combines deep reinforcement learning, graph neural networks, and multi-objective optimization techniques to improve placement quality while reducing design turnaround time. Experimental analysis demonstrates significant improvements in area utilization, wirelength reduction, congestion control, and power efficiency compared with conventional floor planning techniques. The results indicate that AI-driven floor planning represents a promising solution for future semiconductor design automation challenges.
Keywords
VLSI Design Chip Floorplanning Artificial Intelligence Machine Learning Reinforcement Learning Physical Design Automation Wirelength Optimization Electronic Design Automation (EDA).
Article Information
PUBLICATION DETAILS
Review Type:
Double-Blind Peer Review
License:
CC BY-NC 4.0
Volume/Issue:
Volume 02, Issue 7
Review Rounds:
2
Article Type:
Research Article
Publication Date:
Jul 06 2026
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Sindhuja, K. & Shiva, G. (2026). Intelligent Reinforcement Learning-Based Floor Planning Framework for Multi-Objective Optimization in VLSI Physical Design. International Journal of Science, Strategic Management and Technology, 02(7). https://doi.org/10.55041/ijsmt.v2i7.012
Sindhuja, Kole, and Gaddam Shiva. "Intelligent Reinforcement Learning-Based Floor Planning Framework for Multi-Objective Optimization in VLSI Physical Design." International Journal of Science, Strategic Management and Technology, vol. 02, no. 7, 2026, pp. . doi:https://doi.org/10.55041/ijsmt.v2i7.012.
Sindhuja, Kole, and Gaddam Shiva. "Intelligent Reinforcement Learning-Based Floor Planning Framework for Multi-Objective Optimization in VLSI Physical Design." International Journal of Science, Strategic Management and Technology 02, no. 7 (2026). https://doi.org/https://doi.org/10.55041/ijsmt.v2i7.012.
References
[1] N. Sherwani, Algorithms for VLSI Physical Design Automation, Springer, 2019.
[2] S. Sait and H. Youssef, VLSI Physical Design Automation: Theory and Practice, IEEE Press, 1999.
[3] R. H. J. M. Otten, “Automatic Floorplan Design,” Proceedings of the Design Automation Conference, pp. 261–267, 1982.
[4] P. Spindler and F. M. Johannes, “Fast and Accurate Floorplanning,” IEEE Transactions on Computer-Aided Design, vol. 27, no. 11, pp. 1963–1975, 2008.
[5] A. B. Kahng, J. Lienig, I. Markov, and J. Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure, Springer, 2011.
[6] A. Mirhoseini et al., “A Graph Placement Methodology for Fast Chip Design,” Nature, vol. 594, pp. 207–212, 2021.
[7] Y. Bengio, A. Lodi, and A. Prouvost, “Machine Learning for Combinatorial Optimization,” European Journal of Operational Research, vol. 290, no. 2, pp. 405–421, 2021.
[8] V. Nookala and S. S. Sapatnekar, “Machine Learning in Physical Design Automation,” IEEE Design & Test, vol. 37, no. 6, pp. 37–47, 2020.
[9] D. Silver et al., “Mastering the Game of Go with Deep Neural Networks and Tree Search,” Nature, vol. 529, pp. 484–489, 2016.
[10] H. Ren et al., “Chip Placement Optimization with Deep Reinforcement Learning,” IEEE Transactions on CAD, vol. 41, no. 5, pp. 1201–1214, 2022.
[11] J. Cong and M. Pan, “Challenges and Opportunities for Machine Learning in Electronic Design Automation,” IEEE Transactions on CAD, vol. 40, no. 9, pp. 1800–1815, 2021.
[12] K. He, X. Zhang, and J. Sun, “Deep Learning Applications in VLSI Design Automation,” IEEE Access, vol. 10, pp. 81240–81258, 2022.
[2] S. Sait and H. Youssef, VLSI Physical Design Automation: Theory and Practice, IEEE Press, 1999.
[3] R. H. J. M. Otten, “Automatic Floorplan Design,” Proceedings of the Design Automation Conference, pp. 261–267, 1982.
[4] P. Spindler and F. M. Johannes, “Fast and Accurate Floorplanning,” IEEE Transactions on Computer-Aided Design, vol. 27, no. 11, pp. 1963–1975, 2008.
[5] A. B. Kahng, J. Lienig, I. Markov, and J. Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure, Springer, 2011.
[6] A. Mirhoseini et al., “A Graph Placement Methodology for Fast Chip Design,” Nature, vol. 594, pp. 207–212, 2021.
[7] Y. Bengio, A. Lodi, and A. Prouvost, “Machine Learning for Combinatorial Optimization,” European Journal of Operational Research, vol. 290, no. 2, pp. 405–421, 2021.
[8] V. Nookala and S. S. Sapatnekar, “Machine Learning in Physical Design Automation,” IEEE Design & Test, vol. 37, no. 6, pp. 37–47, 2020.
[9] D. Silver et al., “Mastering the Game of Go with Deep Neural Networks and Tree Search,” Nature, vol. 529, pp. 484–489, 2016.
[10] H. Ren et al., “Chip Placement Optimization with Deep Reinforcement Learning,” IEEE Transactions on CAD, vol. 41, no. 5, pp. 1201–1214, 2022.
[11] J. Cong and M. Pan, “Challenges and Opportunities for Machine Learning in Electronic Design Automation,” IEEE Transactions on CAD, vol. 40, no. 9, pp. 1800–1815, 2021.
[12] K. He, X. Zhang, and J. Sun, “Deep Learning Applications in VLSI Design Automation,” IEEE Access, vol. 10, pp. 81240–81258, 2022.
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