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DESIGN OF HIGH SPEED LOW POWER PROCESSOR USING FSM-BASED CONTROL

AUTHORS:
Mansi M Somanache
Mentor
Affiliation
Department of Electronics and Communication Engineering, VTU, Belagavi, India
CC BY 4.0 License:
This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract

The need for faster performance and low power consumption in computer systems is driving the search for better architectures. This paper is the design and implementation of a high-speed low-power 16-bit processor with FSM as a control unit. A Mealy FSM was designed and modified to manage instruction execution across five stages which are fetch, decode, execute, memory access and write back. Combining FSM based control with clock gating proved effective in reducing dynamic power consumption without compromising performance. The processor was modelled in Verilog HDL and synthesized on a Xilinx platform. Functional verification confirmed that all instructions execute correctly. Register values, ALU outputs and Program Counter updates all behaved as expected during simulation.


Power analysis of the on chip design shows a total power consumption of 0.128 W. Dynamic power accounts for 0.106 W of this figure while static leakage power stands at 0.022 W. Timing analysis shows the processor can operate at a maximum frequency of 182 MHz. This is well above the target operating frequency of 68 MHz. These results confirm that the FSM based architecture successfully achieves low power operation while maintaining high speed performance.

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Somanache, M. M. (2026). Design of High Speed Low Power Processor using FSM-Based Control. International Journal of Science, Strategic Management and Technology, 02(6). https://doi.org/10.55041/ijsmt.v2i6.112

Somanache, Mansi. "Design of High Speed Low Power Processor using FSM-Based Control." International Journal of Science, Strategic Management and Technology, vol. 02, no. 6, 2026, pp. . doi:https://doi.org/10.55041/ijsmt.v2i6.112.

Somanache, Mansi. "Design of High Speed Low Power Processor using FSM-Based Control." International Journal of Science, Strategic Management and Technology 02, no. 6 (2026). https://doi.org/https://doi.org/10.55041/ijsmt.v2i6.112.

References
1.Kumar and R. Singh, “Optimization of Finite State Machine (FSM) Based Control Units for Low Power VLSI Applications,” in Proceedings of the International Conference on VLSI and Embedded Systems (ICVES), IEEE, 2024, pp. 112–117.

2.Synopsys , PrimeTime User Guide: Static Timing Analysis, 2023.

3.IEEE Standard for System Verilog – Unified Hardware Design, Specification, and Verification Language, IEEE Std 1800-2023, IEEE, 2023.

4.Chandrakasan, et al., “Low-power CMOS digital design,” IEEE Journal of SolidState Circuits, vol. 27, no. 4, pp. 473-484, 1992.

5.Verma, “Performance Comparison of Hardwired and Microprogrammed Control Units for IoT Processors,” in 2024 IEEE 11th International Conference on Signal Processing and Integrated Networks (SPIN), IEEE, 2024.

6.Saleh, , & Pedram, M. "Analysis and Optimization of Power Consumption in VLSI Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 4, pp. 467-481, April 1994.

7.Wang, Y., Li, Z., & Chen, X. "Dynamic Clock Management for Energy-Efficient Embedded Processors." IEEE Transactions on Circuits and Systems, vol. 70, no. 8, pp. 3214-3225, 2023.

8.Gupta, S., Sharma, V., & Rao, K. "Energy-Efficient Processor Architecture for IoT Sensor Nodes." IEEE Sensors Journal, vol. 24, no. 5, pp. 6120-6130, 2024.
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This article has undergone plagiarism screening and double-blind peer review. Editorial policies have been followed. Authors retain copyright under CC BY-NC 4.0 license. The research complies with ethical standards and institutional guidelines.
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