IMPLEMENTATION OF IMAGE STEGANOGRAPHY ON 32-BIT RISC PROCESSOR
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Modern digitization has resulted in versatility to eradicate the divergence among the types of information travel flanked by the users. It presents a pliable approach for the erratic block size selection in an impulsive mode to spice up the extent of sophistication within the stego algorithm. The plan of this work includes the elimination of key exchange for encoding and improving the safety to a large level without compromising the image quality and embedding capacity. The embedded hardware for stego implementations uses a picture carrier that creates soaring demand on memory, the extremely inhibited resource of embedded devices. The efficiency of the algorithm is to take care of image quality. Different applications are there for various requirements
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Veer, E. & Yadav, E. (2026). Implementation of Image Steganography on 32-Bit RISC Processor. International Journal of Science, Strategic Management and Technology, 02(05). https://doi.org/10.55041/ijsmt.v2i5.377
Veer, Er.Praveen, and Er.Vinod Yadav. "Implementation of Image Steganography on 32-Bit RISC Processor." International Journal of Science, Strategic Management and Technology, vol. 02, no. 05, 2026, pp. . doi:https://doi.org/10.55041/ijsmt.v2i5.377.
Veer, Er.Praveen, and Er.Vinod Yadav. "Implementation of Image Steganography on 32-Bit RISC Processor." International Journal of Science, Strategic Management and Technology 02, no. 05 (2026). https://doi.org/https://doi.org/10.55041/ijsmt.v2i5.377.
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