LOW POWER DESIGN OF A 4-BIT SYNCHRONOUS COUNTER USING 45NM CMOS TECHNOLOGY FOR LOWRANGE COUNTING APPLICATIONS
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This project presents the design of a low-power 4-bit synchronous counter using 45nm CMOS technology. The main aim of this work is to reduce power consumption while maintaining proper speed and performance. The counter is designed using basic CMOS building blocks such as inverters, logic gates, and D flip-flops. These components are first implemented individually and then combined to form the complete counter circuit. In order to improve power efficiency, the Self-Controllable Voltage Level (SVL) technique is used in the flip-flop design. This technique helps in reducing leakage power, especially when the circuit is in idle condition. The entire design is implemented and simulated using Cadence Virtuoso tool. The simulation results show that the counter works correctly and generates the expected binary counting sequence from 0000 to 1111. The output waveforms confirm proper synchronous operation, as all flip-flops are triggered by a common clock signal. The measured power consumption is very low, and the delay is within acceptable limits for low-range counting applications. Overall, the proposed design provides better power efficiency compared to conventional counter designs. This makes it suitable for low-power VLSI applications such as embedded systems and portable electronic devices.
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SHIVANI, G., SRAVANI, C. & RESHMA, E. (2026). Low Power Design of a 4-Bit Synchronous Counter using 45nm Cmos Technology for Lowrange Counting Applications. International Journal of Science, Strategic Management and Technology, 02(05). https://doi.org/10.55041/ijsmt.v2i4.654
SHIVANI, GADARABOINA, et al.. "Low Power Design of a 4-Bit Synchronous Counter using 45nm Cmos Technology for Lowrange Counting Applications." International Journal of Science, Strategic Management and Technology, vol. 02, no. 05, 2026, pp. . doi:https://doi.org/10.55041/ijsmt.v2i4.654.
SHIVANI, GADARABOINA,CH. SRAVANI, and E. RESHMA. "Low Power Design of a 4-Bit Synchronous Counter using 45nm Cmos Technology for Lowrange Counting Applications." International Journal of Science, Strategic Management and Technology 02, no. 05 (2026). https://doi.org/https://doi.org/10.55041/ijsmt.v2i4.654.
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