DESIGN OF HIGH SPEED LOW POWER PROCESSOR USING FSM-BASED CONTROL
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The need for faster performance and low power consumption in computer systems is driving the search for better architectures. This paper is the design and implementation of a high-speed low-power 16-bit processor with FSM as a control unit. A Mealy FSM was designed and modified to manage instruction execution across five stages which are fetch, decode, execute, memory access and write back. Combining FSM based control with clock gating proved effective in reducing dynamic power consumption without compromising performance. The processor was modelled in Verilog HDL and synthesized on a Xilinx platform. Functional verification confirmed that all instructions execute correctly. Register values, ALU outputs and Program Counter updates all behaved as expected during simulation.
Power analysis of the on chip design shows a total power consumption of 0.128 W. Dynamic power accounts for 0.106 W of this figure while static leakage power stands at 0.022 W. Timing analysis shows the processor can operate at a maximum frequency of 182 MHz. This is well above the target operating frequency of 68 MHz. These results confirm that the FSM based architecture successfully achieves low power operation while maintaining high speed performance.
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Somanache, M. M. (2026). Design of High Speed Low Power Processor using FSM-Based Control. International Journal of Science, Strategic Management and Technology, 02(6). https://doi.org/10.55041/ijsmt.v2i6.112
Somanache, Mansi. "Design of High Speed Low Power Processor using FSM-Based Control." International Journal of Science, Strategic Management and Technology, vol. 02, no. 6, 2026, pp. . doi:https://doi.org/10.55041/ijsmt.v2i6.112.
Somanache, Mansi. "Design of High Speed Low Power Processor using FSM-Based Control." International Journal of Science, Strategic Management and Technology 02, no. 6 (2026). https://doi.org/https://doi.org/10.55041/ijsmt.v2i6.112.
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