DESIGN OF A HIGH-PERFORMANCE 32-BIT ALU WITH OPTIMIZED ARITHMETIC UNITS FOR LOW-POWER VLSI SYSTEMS
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The basic computational unit of high performance processors and digital signal processor systems is the Arithmetic Logic Unit (ALUs). For implementing high speed and low power VLSI system, fast arithmetic circuits with higher performance and less resources are required. The design and implementation of high speed 32-bit ALU based on Han-Carlson parallel prefix adder and Radix-4 Booth encoded Dadda multiplier is discussed in this paper. The designed ALU is a combination of fast arithmetic computation block and optimized logic control circuits in an effort to reduce the propagation delay and power consumption. It is a fast propagation characteristic combination of Kogge-Stone and Brent-Kung adder using Han-Carlson adder. For better efficiency and less delay Radix-4 Booth encoded Dadda multiplier is proposed which reduces the number of partial products to the minimum with the help of Booth radix-4 multiplication and less multiplier delay. The whole ALU is designed, synthesized in Verilog HDL and FPGA design flow, and CMOS design flow. Results illustrates that designed ALU provides a critical delay of 2.65 ns, power consumption of 14.8 m W and PDP of 39.22p J, which makes it better than the existing ALU designs.
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Goral, S. (2026). Design of a High-Performance 32-Bit Alu with Optimized Arithmetic Units for Low-Power Vlsi Systems. International Journal of Science, Strategic Management and Technology, 02(6). https://doi.org/10.55041/ijsmt.v2i6.117
Goral, Snehal. "Design of a High-Performance 32-Bit Alu with Optimized Arithmetic Units for Low-Power Vlsi Systems." International Journal of Science, Strategic Management and Technology, vol. 02, no. 6, 2026, pp. . doi:https://doi.org/10.55041/ijsmt.v2i6.117.
Goral, Snehal. "Design of a High-Performance 32-Bit Alu with Optimized Arithmetic Units for Low-Power Vlsi Systems." International Journal of Science, Strategic Management and Technology 02, no. 6 (2026). https://doi.org/https://doi.org/10.55041/ijsmt.v2i6.117.
References
[1] A. Sharma and P. K. Singh, "Comparative Analysis of Parallel Prefix Adders for High-Speed Datapaths," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 4, pp. 1105-1109, Apr. 2024.
[2] M. Rahman and A. Harris, "Power-Delay Optimization Using Hybrid Han-Carlson Addition Topologies," IEEE Journal of Solid-State Circuits, vol. 59, no. 8, pp. 2240-2251, Aug. 2024.
[3] L. Wang and J. Chen, "Design Space Exploration of Tree-Based Multiplier Architectures," IEEE Transactions on Computers, vol. 74, no. 1, pp. 88-101, Jan. 2025.
[4] S. Beura and P. Saha, "Limitations of Approximate Computing in Mission-Critical Arithmetic Logic Units," IEEE Transactions on Emerging Topics in Computing, vol. 13, no. 3, pp. 450-462, Mar. 2025.
[5] K. Patel and V. Desai, "Dynamic Power Suppression in FPGA Datapaths Utilizing RTL-Level Clock Gating," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 44, no. 5, pp. 1320-1332, May 2025.
[6] R. Kumar, T. S. Reddy, and M. V. Desai, "Design and Implementation of a High-Speed Exact Radix-4 Booth Multiplier with Dadda Reduction for Precision VLSI Datapaths," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 34, no. 2, pp. 210-222, Feb. 2026.
[7]Birla, S., Neha Singh, Jeevani G.S.N, Kumawat, R., and Srinivasulu, A, “Unified Multimodal 64-Bit arithmetic logic unit for high-performance computing architectures”, Journal of VLSI circuits and systems, 7(2), 1–8, 2025.
[8]Sutrakar, M., and Tiwari, S, “Survey of arithmetic and logical unit based on reversible logic gate structure”, International journal of research and technology, 11(3), 22-26, 2023.
[9]Kumar, Mr K. Naveen, B. Jyoshna, A. Ramu, M. Lahari, S. Lakshmi Kanth, and M. Akshitha. "Design of arithmetic logic unit using reversible logic gates." Research digest on engineering management and social innovations2, no. 4, 215-225, 2026.
[10]G.M.V. Prasad, SasiNakka, SatishKatta, JahnaviDesamsetti, and Mani SaiAdimulam. “A 32-Bit ripple-ling hybrid carry adder”. Fringe multiengineering proceedings (FMEP, ISSN: 3107-6149), 2(1). 2026.
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